Manufacturing method of thin film transistor and display array substrate using same
US8980704B1 · kind B1 · utility
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3References
20Claims
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Key dates
| Filing date | Aug 25, 2014 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.