Semiconductor device and field effect transistor

US8981434B2 · kind B2 · utility

Assignee

• RENESAS ELECTRONICS CORPORATION · JP

Inventors

• Hironobu Miyamoto · Tokyo, JP
• Yasuhiro Okamoto · Tokyo, JP
• Yuji Ando · Tokyo, JP
• Tatsuo Nakayama · Yokohama, JP
• Takashi Inoue · Hachioji, JP
• Kazuki Ota · Tochigi, JP
• Kazuomi Endo · Hiroshima, JP

Key dates

• Filing date: Jun 23, 2010
• Grant date: Mar 17, 2015
• Expiry date: Oct 12, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The …