Semiconductor memory device and manufacturing method thereof
US8981455B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
In accordance with an embodiment, a semiconductor memory device includes a substrate with a semiconductor layer and memory cells on the semiconductor layer. Each memory cell includes a laminated body on the semiconductor layer, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body includes a tunnel insulating film and a floating gate subsequently laminated in a direction vertical to a front surface of the substrate for N (a natural number equal to or above 2) times. A dimension of a top face of any floating gate in a second or subsequent layer is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer in at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.