Three-dimensional semiconductor devices and methods of fabricating the same
US8981458B2 · kind B2 · utility
8Cited by
0References
22Claims
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Key dates
| Filing date | Nov 7, 2011 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Dec 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.