ESD protection structure and ESD protection circuit

US8981483B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Paul Ouyang · Shanghai, CN
• Wenjun Weng · Shanghai, CN
• Huijuan Cheng · Shanghai, CN
• Jie Chen · Shanghai, CN
• Hongwei Li · Burnaby, CA

Key dates

• Filing date: Mar 27, 2014
• Grant date: Mar 17, 2015
• Expiry date: Mar 27, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/815

Abstract

An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. Second doped base regions discretely located in a fourth region of a first P-type well region are P-type doped and connected to the external trigger-voltage adjustment circuit. A first N-region is located in the fourth region, surrounding the second doped base regions, and connected to the I/O interface terminal. A second N-region is located in the fourth region, surrounding the first N-region and the second doped base regions, and connected to the ground terminal.