Shift register and active matrix device
US8982015B2 · kind B2 · utility
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4References
6Claims
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Key dates
| Filing date | Mar 31, 2009 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Aug 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0492
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.