Memory having read assist device and method of operating the same
US8982609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2012 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Mar 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.