Low power static random access memory
US8982610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Jun 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.