Patent · US Active

Jitter tolerant receiver

US8982999B2 · kind B2 · utility

2Cited by

13References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Kiriti Bhagavathula · Cameron Park, US
Chunyu Zhang · Longbeilingcun, CN
Steven Peterson · Sacramento, US

Key dates

Filing date	Sep 30, 2012
Grant date	Mar 17, 2015
Priority date	—
Expiry date	Oct 15, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/03878
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.