Variance analysis for translating CUDA code for execution by a general purpose processor
US8984498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2009 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | May 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0253
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.