Method of manufacturing Si-based high-mobility group III-V/Ge channel CMOS

US8987141B2 · kind B2 · utility

Assignee

• INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Xuliang Zhou · Beijing, CN
• Hongyan Yu · Beijing, CN
• Shiyan Li · Beijing, CN
• Jiaoqing Pan · Beijing, CN
• Wei Wang · Tangxia, CN

Key dates

• Filing date: Mar 21, 2014
• Grant date: Mar 24, 2015
• Expiry date: Mar 21, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/08
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.