Thin film transistor array panel and the method for manufacturing thereof
US8987741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2011 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Jan 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/40
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided is a thin film transistor array panel that includes: a substrate; a gate line and a data line formed on the substrate and at least partially defining a pixel area; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor and formed in the pixel area; a first common electrode formed under the pixel electrode; a second common electrode formed on the pixel electrode. The pixel area includes an upper pixel area and a lower pixel area, the first common electrode is formed in the upper pixel area, and the second common electrode is formed in the lower pixel area. The pixel electrode includes an upper pixel electrode formed in the upper pixel area and a lower pixel electrode formed in the lower pixel area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.