Three dimensional semiconductor memory devices and methods of manufacturing the same
US8987803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Nov 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.