Balanced stress assembly for semiconductor devices
US8987875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Sep 25, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49169
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The material and thicknesses of the substrates and lead frames are selected so stress experienced by the electronic devices caused by changes in temperature of the assembly are balanced from the center of the assembly, thereby eliminating the need for balancing stresses at a substrate level by applying substantially matching metal layers to both sides of the substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.