System, a method and a computer program product for electronic sub-integer frequency division
US8988119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Jan 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic sub-integer frequency divider circuit, including: a phase rotator circuit, a clock circuitry, a pulse generator which is configured to: (a) receive a plurality of signals having a period TP and of different phases; (b) based on a control command, to process a second clock signal and one or more of the plurality of signals, to produce a second signal which includes S pulses in each period TP; and (c) process the second signal and a first clock signal to produce a regulating signal by which the phase rotator circuit is controlled; and an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.