Patent · US Active

Small area low power data retention flop

US8988123B2 · kind B2 · utility

1Cited by

18References

8Claims

0Family size

Assignee

NVIDIA Corporation · US

Inventors

Ge Yang · Beijing, CN
Hwong-Kwo Lin · Palo Alto, US
Xi Zhang · Ottawa, CA
Jiani Yu · Fremont, US

Key dates

Filing date	Dec 14, 2012
Grant date	Mar 24, 2015
Priority date	—
Expiry date	Dec 14, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/0375
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.