Operating method of a nonvolatile memory device
US8988928B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 22, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Sep 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a multi-bit-per-cell nonvolatile memory device, e.g., first and second variable resistance memory cells connected to one of word lines. The operating method may include receiving first to fourth data sequentially, providing a first program current to the first variable resistance memory cell to program the first and second data to the first variable resistance memory cell, and providing a second program current to the second variable resistance memory cell to program the third and fourth data to the second variable resistance memory cell after verifying whether an actual resistance of the programmed first variable resistance memory cell is within an intended resistance distribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.