Time processing method and circuit for synchronous SRAM
US8988932B2 · kind B2 · utility
1Cited by
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15Claims
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Key dates
| Filing date | Oct 18, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Nov 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal. The circuit for a synchronous SRAM includes: a wordline decoder, a timing generator, a wordline controller, a wordline pulse width generator, a memory cell array, and a sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.