Compensation scheme for non-volatile memory
US8988936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2014 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Oct 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.