Memory macro with a voltage keeper
US8988948B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Sep 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.