Pipeline method and system for switching packets
US8989202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Feb 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1546
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.