Efficient memory management for parallel synchronous computing systems
US8990497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Dec 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies relating to efficient memory management for parallel synchronous computing systems are disclosed. Parallel synchronous computing systems may include, for example, a host, a memory management subsystem, and an array of processing units adapted to execute in parallel. Memory management may be implemented at least in part via the memory management subsystem. A memory management subsystem may include one or more memory subsystem layers deployed between the host and the array of processing units. Each memory subsystem layer may have a local memory accessible by entities (whether the host or another layer) above the memory subsystem layer; and a memory controller adapted to manage communications between the entities (whether another layer or the processing units in the array) below the memory subsystem layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.