Post-silicon validation using a partial reference model
US8990622B2 · kind B2 · utility
2Cited by
7References
10Claims
0Family size
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Key dates
| Filing date | Jul 29, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Apr 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.