Patent · US Active

Method of fabricating a charge-trapping gate stack using a CMOS process flow

US8993457B1 · kind B1 · utility

456Cited by
12References
20Claims
0Family size

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Key dates

Filing dateSep 18, 2014
Grant dateMar 31, 2015
Priority date—
Expiry dateSep 18, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/02337
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.