Patent · US Active

Method and arrangement for generating a clock signal by means of a phase locked loop

US8994418B2 · kind B2 · utility

0Cited by

13References

4Claims

0Family size

Assignee

Technische Universitaet Dresden · DE

Inventors

Sebastian Hoeppner · Dresden, DE
Stefan HAENZSCHE · Dresden, DE

Key dates

Filing date	Feb 25, 2014
Grant date	Mar 31, 2015
Priority date	—
Expiry date	Feb 25, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/091
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.