Higher-order phase noise modulator to reduce spurs and quantization noise
US8994420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | May 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3042
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.