Energy efficient flip-flop with reduced setup time
US8994429B1 · kind B1 · utility
0Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of a flip-flip circuit are disclosed that may allow a reduction in data setup time and lower switching power. The flip-flop circuit may include an input circuit, an output circuit, a clock circuit, and a feedback circuit. The clock circuit may be operable to generate internal clocks dependent upon received data, and the generated internal clocks may enable the feedback and input circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.