Method and apparatus for generating on-chip clock with low power consumption
US8994433B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 13, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jan 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fully on-chip clock generator on an integrated circuit (“IC”) includes a frequency detector for receiving a reference current and providing a first voltage; an error integrator for receiving the first voltage from the frequency detector, comparing it with a reference voltage, and providing a control voltage; a voltage controlled oscillator (“VCO”) for receiving the control voltage from the error integrator, and providing an output clock; and a logic controller on the IC, coupled between the VCO and the frequency detector, and generating logic control signals for controlling the frequency detector. The fully on-chip clock generator requires no external crystal, but its power consumption is significantly lower than a relaxation oscillator that generates the same clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.