Low-noise high efficiency bias generation circuits and method
US8994452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2009 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Aug 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45642
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias gen…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.