Oscillator arrangement for generating a clock signal
US8994459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jul 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided an oscillator arrangement for generating a clock signal. The oscillator arrangement comprises a current controlled oscillator, a frequency to voltage converter, and an operational amplifier. The oscillator arrangement is connectable to a supply voltage source. In one embodiment, the oscillator arrangement may achieve a stable clock frequency insensitive to supply and temperature variation with low current consumption and low area. This may be achieved by using Vref and Vout as input signals to the operational amplifier, both signals being directly derived from the supply voltage. In a further embodiment, a trimming resistor may be used in the frequency to voltage converter for adjusting the frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.