Latch circuit and display device using the latch circuit
US8994704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jul 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch circuit includes an input transistor, a retention capacitor connected between an electrode of the input transistor and a first latch control line, a first transistor having an electrode connected to the first latch control line and a gate connected to the electrode of the input transistor, a second transistor having a gate connected to another electrode of the first transistor and an electrode is connected to the second latch control line, a third transistor having a gate connected to the another electrode of the first transistor and an electrode connected to another electrode of the second transistor and another electrode connected to an output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.