Passive power factor correction circuit
US8995153B2 · kind B2 · utility
0Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jun 1, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a passive power factor correction circuit. The passive power factor correction circuit comprises: a filtering device being used for decreasing high order harmonic of an input current; a resonance device being coupled to the filtering device for controlling operation time of the input current; and a suppression device being coupled to the resonance device for suppressing ripple of the input current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.