Resistive memory cell
US8995165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of the RRAM by using an intrinsic floating effect of the SOI substrate. The present invention utilizes a floating effect of a SOI device, in which under the same width/length ratio, a MOS transistor over a SOI substrate can provide larger source/drain current than a MOS transistor over a bulk silicon, so that the area occupied by the selection transistor is reduced, which is advantageous to the integration of the RRAM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.