Multi-core processor system, cache coherency control method, and computer product
US8996820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Mar 2, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.