Alarm-based power saving mode for electronic device where a power latch controls power switch based on a control value
US8996898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jan 9, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to an alarm-based power saving mode and associated system implemented on a device for a microprocessor or a telematics circuitry, and more particularly, to an alarm and powered-up microprocessor-driven power latch for disabling a power source to a microprocessor or telematics circuitry at a power switch. A microprocessor and/or telematics circuitry are powered down by an instruction step from the microprocessor or the telematics circuitry by using a power switch to cut off power. The switch is controlled by a power latch, which is regulated by a wake-up value given to an alarm to enable the power latch and exercise power switch control, as well as by a value given directly by the microprocessor to enter the powered down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.