Apparatus for monitoring operating conditions of a logic circuit
US8996937B2 · kind B2 · utility
9Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jul 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.