Error correction code rate management for nonvolatile memory
US8996961B2 · kind B2 · utility
5Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jun 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.