N-way memory barrier operation coalescing
US8997103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Mar 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups may be coalesced with the first memory barrier to produce a coalesced memory barrier that represents memory barrier operations for multiple thread groups. When the coalesced memory barrier is being processed, execution of subsequent memory operations for the different thread groups is also suspended. However, memory operations for other thread groups that are not affected by the coalesced memory barrier may be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.