Protection layer for halftone process of third metal
US8999771B2 · kind B2 · utility
1Cited by
71References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Sep 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.