Semiconductor structure
US9000569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Dec 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.