Implementation of related clocks
US9000801B1 · kind B1 · utility
5Cited by
48References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jun 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.