Fractional spur reduction using controlled clock jitter
US9000815B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.