System and method for controlling at least two power semiconductors connected in parallel
US9000827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2010 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Sep 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/325
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A system includes at least two power semiconductor chips being connected in parallel and including each a gate terminal for switching the power semiconductor chip in a blocking-state by a first gate voltage and for switching the power semiconductor chip in a conducting-state by a second gate voltage. The system includes further a control device adapted for applying the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips. The control device is adapted for applying a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip when a power semiconductor chip fails, and that the third gate voltage is higher than the second gate voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.