Substrate assembly provided with capacitive interconnections, and manufacturing method thereof
US9001521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jun 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element, and the second bump being ohmically coupled to the second interconnection element and to the fourth interconnection element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.