6T static random access memory cell, array and memory thereof
US9001571B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2014 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jan 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access transistor. The first inverter and second inverter respectively include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor and a second pull-down transistor. The first pull-down and pull-up transistors each have a drain terminal mutually coupled to form a first node. The second pull-down and pull-up transistors each have a drain terminal mutually coupled to form a second node. The first and second access transistors each have a gate terminal respectively coupled to a first word line and a second word line. When the first word line provides on signals to turn on the first access transistor, the second low voltage supply provides a first differential voltage simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.