Memory device including repair circuit and repair method thereof
US9001601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | May 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array. The repair circuit also includes a row address comparison unit configured to compare the row address of the defective cell with a row address of a first access cell received from the outside, and to output a first row match signal when the defective cell's row address matches the row address of the first access cell, and a column address comparison unit configured to compare the column address of the defective cell with a column address of the first access cell received from the outside, and to output a first column address replacement signal if the column address of the defective cell is the same as the column address of the first access cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.