Parallel receiver interface with receiver redundancy
US9001842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | May 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications parallel bus receiver interface having N data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. An input switching network is configured to receive and couple N parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two adjacent bit receivers. A calibration device calibrates one of the two adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through each of N+1 receivers to periodically recalibrate each receiver (one at a time) while N inputs are processed continuously and uninterrupted. The interface is configured such that another receiver is receiving the same data as the receiver that is being calibrated, and the qualifications for receiver calibration can be made with minimal circuit overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.