Memory controller, devices including the same, and operating method thereof
US9003262B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Oct 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the number of error bits in data programmed to each of the blocks, and creating a combinational block by combining a first block from the first group with a second block from the second group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.