Software breakpoints with tailoring for multiple processor shared memory or multiple thread systems
US9003376B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2002 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Dec 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides methods for executing instructions in a processor to facilitate the debugging of digital systems. In these methods, a halt identifier field is associated with every instruction that holds an encoding specifying an action to be performed by a processor. As instructions are executed on a processor, actions are performed by the processor based on the value of the halt identifier field of the executed instructions. In an embodiment, when each instruction is executed, the contents of the halt identifier field are compared to a pre-selected identifier value and the processor is halted if the values are the same. In a multiprocessor system, the pre-selected identifier may be a unique value that identifies the processor such that when the halt identifier field is equal to that value, the processor will halt. In a single processor system, the pre-selected value may be used to identify a task, a process, or a thread of execution that is to be halted when a halt identifier field with that value is encountered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.