CMOS transistor and method for fabricating the same
US9006059B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Oct 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0231
Abstract
The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming channels, which comprises: depositing an amorphous silicon layer on a substrate, and crystallizing the amorphous silicon layer into a poly-silicon layer; implanting boron atoms into the poly-silicon layer and then forming an N channel region and a P channel region by etching the poly-silicon layer implanted with the boron atoms; forming a photoresist-partially-retained region corresponding to the N channel region and a photoresist-completely-retained region corresponding to the P channel region through a single patterning process; and removing the photoresist in the photoresist-partially-retained-region and retaining a part of the photoresist in the photoresist-completely-retained region using an ashing process, implanting phosphorus atoms through ion implantation thereby forming an N channel and a P channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.